Chris Johnston

PhD (Computer Systems Engineering)

BE(Hons) (Information and Telecommunications)

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Publications

Journal and Conference Publications in reverse chronological order. Further information and paper links can be found at the Massey University School of Engineering and Advanced Technology Signal Processing Research Group's publications page.

PhD Thesis

Journal Publications

2006

Conference Publications

2010

  • C.T. Johnston, D. Bailey, and P. Lyons, "Notations for multiphase pipelines", in 5th IEEE International Symposium on Electronic Design, Test and Applications (DELTA 2010), Ho Chi Minh City, Vietnam, 212-216 (13-15 January, 2010).
  • D. Bailey and C. Johnston, "Algorithm transformation for FPGA implementation", in 5th IEEE International Symposium on Electronic Design, Test and Applications (DELTA 2010), Ho Chi Minh City, Vietnam, 77-81 (13-15 January, 2010).

2009

  • C.T. Johnston, P. Lyons, and D. Bailey, "Paper based evaluation and overview of a visual language for real time image processing on FPGAs", in 10th International Conference of the NZ chapter of the ACM's Special Interest Group on Human-Computer Interaction (CHINZ 2009), Auckland, NZ, 85-92 (6-7 July, 2009).

2008

  • N. Ma, D. Bailey, and C. Johnston, “Optimised single pass connected components analysis”, in International Conference on Field Programmable Technology, Taipei, Taiwan, 185-191 (8-10 December, 2008).
  • D.G. Bailey, C.T. Johnston, and N. Ma, “Connected components analysis of streamed images”, in International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 679-682 (8-10 September, 2008).
  • C.T. Johnston, P. Lyons, and D.G. Bailey, “A Visual Notation for Processor and Resource Scheduling”, in IEEE International Symposium on Electronic Design, Test and Applications(DELTA 2008), Hong Kong, (23-25 January, 2008).
  • C.T. Johnston and D.G. Bailey, “FPGA implementation of a Single Pass Connected Components Algorithm”, in IEEE International Symposium on Electronic Design, Test and Applications(DELTA 2008), Hong Kong, (23-25 January, 2008).

2007

  • D.G. Bailey and C.T. Johnston, “Single Pass Connected Components Analysis”, in Image and Vision Computing New Zealand, Hamilton, New Zealand, 217-222 (5-7 December, 2007).

2006

  • C.T. Johnston, D.G. Bailey, and P. Lyons,”Towards a Visual Notation for Pipelining in a Visual Programming Language for Programming FPGAs”, in 7th International Conference of the NZ chapter of the ACM’s Special Interest Group on Human-Computer Interaction (CHINZ 2006), Christchurch, NZ, ACM International Conference Proceeding Series, 158: 1-9 (July 6-7, 2006).
  • K.T. Gribbon, C.T. Johnston, D.G. Bailey,”Formalizing Design Patterns for Image Processing Algorithm Development on FPGAs”, Proceedings of the third IEEE International Workshop on Electronic Design, Test, and Applications (Delta 2006), Kuala Lumpur, Malaysia, pp 47-53 (17-19 January, 2006)
  • Donald Bailey, Kim Gribbon, Chris Johnston, “GATOS: A Windowing Operating System for FPGAs”, Proceedings of the third IEEE International Workshop on Electronic Design, Test, and Applications (Delta 2006), Kuala Lumpur, Malaysia, pp 405-409, (17-19 January, 2006)

2005

  • C.T. Johnston, D.G. Bailey, K.T. Gribbon, “Optimisation of a colour segmentation and tracking for real-time FPGA implementation”, Image and Vision Computing New Zealand, Dunedin, pp 422-427 (28-29 November, 2005)
  • Christopher T. Johnston, Kim T. Gribbon, Donald G. Bailey, “FPGA Based Remote Object Tracking for Real-time Control”, International Conference on Sensing Technology, Palmerston North, pp 66-71 (21-23 November 2005)
  • K.T. Gribbon, C.T. Johnston, D.G. Bailey, “Formalizing Design Patterns for Image Processing Algorithm Development on FPGAs”, IEEE Tencon’05, Melbourne, Australia, (21-24 November 2005)

2004

  • K. Gribbon, D.G.Bailey, C.T. Johnston, “Colour edge enhancement”, Proceedings Image and Vision Computing New Zealand 2004, Akaroa, New Zealand, pp 291-296 (November 2004)
  • C.T. Johnston, D.G.Bailey, P. Lyons, K.T. Gribbon, “Formalisation of a Visual Environment for Real Time Image Processing in Hardware (VERTIPH)”, Proceedings Image and Vision Computing New Zealand 2004, Akaroa, New Zealand, pp 297-302 (November 2004)
  • C.T. Johnston, K.T. Gribbon, D.G. Bailey, .Implementing Image Processing Algorithms on FPGAs., Proceedings of the Eleventh Electronics New Zealand Conference, ENZCon.04, Palmerston North, New Zealand, pp 118-123 (November 2004)

2003

  • C.T. Johnston, D.G. Bailey, A Real-time FPGA Implementation of a Barrel Distortion Correction Algorithm.,Projects Journal, 12: 91-96 (2003)
  • K.T. Gribbon, C.T. Johnston, D.G. Bailey. A Real-time FPGA Implementation of a Barrel Distortion Correction Algorithm with Bilinear Interpolation., Proceedings of Image and Vision Computing New Zealand, Palmerston North, New Zealand, pp 408-413 (November 2003).

Reports

2003